In the highly competitive VLSI (very large scale integration) industry, the insatiable desire for higher chip performance continuously pushes the envelope in integrated circuit (IC) design methodologies. A new design methodology means new design requirements and targets, such as timing, signal integrity (SI), yield, manufacturability, etc. Because products that are late to the market are likely to lose revenue and market share, as the product life cycles become shorter and shorter, the design time also becomes very important. Consequently, achieving a specified chip performance, which continues to increase, within a designated design time frame, which seems to keep shrinking, present a constant challenge to IC designers and engineers alike.
The flow for designing an integrated circuit can be roughly divided into the logical design phase and the physical design phase. The logical design phase includes several design stages: from the design specification to architectural behavioral design stage, to the register transfer level (RTL) design stage, to the gate design stage, after which the logical IC design is ready for the physical design phase. The physical design phase includes floor planning, placement, and routing, which produces the physical IC design layout.
To help defining design parameters and eliminate incorrect design paths early on in the logical design phase, several commercial logic-synthesis tools from companies such as Synopsys offer digital chip analysis and design planning at the gate level. Analysis at the gate level is sufficient for design complexities at around 50,000 to 100,000 gates. Unfortunately, system-on-a-chip (SOC) complexities reaching into the tens of millions of gates have made gate-level design planning inadequate.
Several companies, such as Synopsys, Cadence, Magma, Tera Systems, TransEDA, Sente Inc., to name a few, offer RTL design and planning tools to help IC designers make certain chip-design decisions before logic synthesis. Given an RTL description, these tools can provide an early prediction of how a sub-chip behaves within the context of the entire chip. Without the structural information that is part of a gate-level design description, however, it is very difficult to estimate design parameters, such as on-chip timing delays, power dissipation, and chip size. Indeed, because of the lack of precise geometry information of wires, design verification in stages before detail routing inevitably all must base on some predictions.
In an IC design flow, verification and optimization is used in almost every stage. At the end of physical design flow, the routed layout must again be verified for the specified design requirements. According to the verification results, the routed layout almost always needs to be further optimized to meet various targets. However, due to the high complexity and large scale of the designs, performing an optimization after detail routing (i.e., post-layout optimization) is very difficult and continues to be a challenge today.
In a routed layout, all layout elements including the wire paths are represented by geometrical shapes such as polygons that have precise shape and location. Because layout modifications must not introduce any design rule violation into the design, almost every wire path is restrained by surrounding wires and other layout elements. Whether one modification can be achieved depends entirely on the available local layout resource. In most cases, the local resource is inadequate for any layout change.
The difficulty in post-layout optimization and the fact that engineers generally like to make design decisions as early in the design process as possible explain the lack of viable post-layout optimization tools on the market, contrasting the number of various logical design and planning tools as well as physical placement and routing tools readily available today.
Some known placement and routing tools have the ability to handle engineering change orders (ECOs). This ability allows the designer to go back to the physical design stages like placement or routing to impose more design constraints that represent the preferred layout modifications. The downside is that a typical back-end design iteration usually takes days to process and compute. This approach therefore places a heavy burden on the design time issue as mentioned before. Another drawback is that, due to the indirect approach, the additional design iteration cannot guarantee those layout modifications.
Generally, in the ultra deep sub-micron era, performing the verification and optimization in the early stages of the physical design phase without the precise net wiring, i.e., before detail routing, the verification result is far from the actual layout. Furthermore, verification error is almost unavoidable, which makes the subsequent optimization less effective and useful.
Clearly, there is a need in the art for a new optimization tool, system, and method that enables IC designers to achieve a specified chip performance within a designated design time frame after detail routing without the aforementioned drawbacks and that overcomes the difficult challenges in post-layout optimization. The present invention addresses this need.